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Paper title: A SINGLE-ENDED READ DISTURB-FREE PPN BASED 9T SRAM CELL

Author(s): SHIV RAM MANSORE, RADHESHYAM GAMAD, DEEPAK KUMAR MISHRA,

Abstract:

This paper presents a single-ended PPN based nine transistor (9T) SRAM cell. Single ended structure enables lower dynamic power consumption as compared to differential SRAM cells. Also, a single ended cell needs half the no. of write drivers as compared to differential design. Proposed design is immune to soft errors as it supports bit-interleaving architecture. Simulation is done on Semi-Conductor Laboratory (SCL) 180 nm CMOS technology on Cadence. The simulation results show that the proposed 9T cell achieves 1.14 and 1.77 larger read static noise margin (RSNM) as compared to ST-2 and conventional 6T cells respectively, at 0.8 V. It consumes 0.46 lower write power as compare to ST-2 cell. Leakage power consumption of the cell is 0.80 lesser than ST-2 cell at 0.8 V.

Keywords: Leakage power, Read delay, Static random access memory (SRAM), Static noise margin (SNM), Write delay

Year: 2018 | Tome: 63 | Issue: 3 | Pp.: 295-299

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