This paper presents the design of a CMOS voltage reference circuit. In the past, the design of a CMOS voltage reference circuit consisted of a lot of active and passive devices or required an external startup circuit. Therefore, this research presents the design of a voltage reference circuit using all CMOS without parasitic bipolar junction transistors (BJT) and passive devices, which cause loss of power and consume a large chip area. It can be operated without external startup circuit. The result of PSPICE (personal simulation program with IC emphasis) simulation program has been verified that the circuit can operate with stability. The supply voltage is only 1.8 V, reference voltage levels of about 259 ± 2.5 mV, the standard temperature coefficient of 95.15 ppm/ºC, ranges from –20 to 100 ºC and a low power dissipation of 2.93 μW.

Keywords: CMOS, Voltage reference, Subthreshold, Temperature compensation, Low voltage, Low power