This paper describes an efficient hardware implementation for the address generation block used in the interleaving procedure associated with the channel turbo coding/decoding modules in the long term evolution (LTE) standard. The solution exploits key arithmetic properties of the corresponding equation to perform the address computation in a recursive manner. The proposed method replaces divisions and multiplications by comparisons and subtractions. The new implementation model targets a Xilinx Virtex 5 XC5VFX70T field programmable gate array (FPGA) device.

Keywords: Long term evolution (LTE), Turbo codes, Interleaver, Field programmable gate array (FPGA) implementation