This paper describes an efficient Field programmable gate array (FPGA) implementation of a convolutional turbo code (CTC) decoder for long term evolution (LTE) standard, release 8, using maximum logarithmic – maximum a posteriori probability (Max Log MAP) algorithm. The considered coding rate is 1/3 (the native coding rate), the puncturing procedure not being taken into discussion here, and the number of turbo iterations is chosen as 3, without reducing the generality of the reported results. The hardware implementation targets a Xilinx Virtex 5 XC5VFX70T device, from a Xilinx ML507 evaluation board.

Keywords: Long term evolution (LTE), Turbo codes, Field programmable gate array (FPGA) implementation, Maximum logarithmic (Max log) - maximum a posteriori probability (MAP)