This paper deals with diagnosing the failure effects in applying electrostatic charges on a model based on MOSFET transistors. In this regard, the work highlights the performance of a One-bit full adder CMOS structure by applying high stresses on one of its inputs. The testing results are carried out using the CADENCE IC 5.3 software package by considering the alternative electrostatic discharge implementation of the transmission line pulse method. The functionality of the structure was improved by adding several electronic components with electrostatic discharge protective properties

Keywords: Electrostatic discharge, One-bit full adder, Transmission line pulse method, Circuit design