In this paper, we present a solution for the optimization of a power supply consumption using an evolvable hardware structure in order to command a voltage regulator. Traditional power regulators use a fixed time division for obtaining the command pulse that is necessary to generate the linear output voltage. By using the variable time division, we can decrease the nonlinear output voltage time and reduce the consumption during nonlinear mode operation. In our case, variable time division uses an evolvable hardware command system based on a hardware genetic algorithm and a reconfigurable circuit. The aim of our paper is to study how to reduce the response time for the power regulator using a parallel hardware solution. One single chip, available in commercial edition (Spartan 3 FPGA family), integrates the entire command solution.

Keywords: Evolvable hardware, Boolean function network, Field programmable gates array (FPGA), Evolvable power regulator