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Paper title: SETTLING-TIME-ORIENTED DESIGN PROCEDURE FOR TWO-STAGE AMPLIFIERS WITH CURRENT-BUFFER MILLER COMPENSATION
Author(s): ANDREA PUGLIESE, FRANCESCO AMOROSO, GREGORIO CAPPUCCINO, GIUSEPPE COCORULLO,
Abstract: A novel design procedure for two-stage operational amplifiers (op-amps) with currentbuffer
Miller compensation (CBMC) is proposed. The method is based on equations
which relate both bias current and aspect ratio of transistors to the main amplifier
parameters. The important innovation of the procedure is the definition of a systematic
strategy to achieve the desired settling time by performing the op-amp dynamic
behaviour optimization, which is badly needed in high-performance discrete-time
applications. To prove the effectiveness of the proposed approach, a design example of
a CBMC op-amp in 0.35 μm CMOS technology is presented.
Keywords: Operational amplifiers, Settling time. Year: 2009 | Tome: 54 | Issue: 4 | Pp.: 375-384
Full text : PDF (242 KB) |
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